1. Field of the Invention
The present invention relates to triple self-aligning non-volatile memory and a method for manufacturing non-volatile memory, and particularly relates to a method for manufacturing non-volatile memory with a stabilized floating gate shape.
2. Description of the Related Art
Flash memory as been developed as a type of non-volatile memory. Flash memory has a configuration wherein a great number of cells are arrayed, with each cell having a standard MOS transistor source drain gate (control gate), and also a floating gate which is embedded in an insulating film and is in an electrically floating state. Upon the source and substrate being grounded and voltage being applied to the control gate and drain, electrons travel from the source toward the drain, and some of these electrodes traverse the insulating film into the floating gate, so the floating gate is negatively charged. Thus, writing is performed. Also, drawing the electrons to the control gate or drain across the insulating film makes the floating gate electrically neutral. Thus, erasing is performed.
With flash memory, the overall degree of integration can be improved, since each cell can be made smaller. Accordingly, methods for manufacturing fine cells with high precision have been proposed (e.g., Document “2000 Symposium on VLSI Technology Digest of Technical Papers” pp 120-121, and U.S. Pat. No. 6,429,075).
FIGS. 1A through 1D, 2A through 2D, 3A through 3D, and FIG. 4 are cross-sectional diagrams illustrating a conventional method for manufacturing flash memory described in the aforementioned Document, in order to steps.
First, as shown in FIG. 1A, a coupling oxide film COX101 is formed to a thickness of 10 nm on a p-type silicon substrate 101 by CVD (Chemical Vapor Deposition). Next, a polysilicon film PS101 around 150 to 200 nm in thickness is formed on the coupling oxide film COX101, followed by a silicon nitride film SN102 around 350 to 400 nm in thickness being formed on the polysilicon film PS101. Next, a resist (not shown) is formed on the silicon nitride film SN102, and patterned in slits. The patterned resist is masked, and the silicon nitride film SN102 is selectively removed by dry etching, so as to form openings 102 from which the polysilicon film PS101 is partially exposed.
At this time, the area around the surface of the polysilicon film PS101 is over-etched due to the dry etching of the silicon nitride film SN102, as shown in FIG. 1B. Consequently, a bowl-shaped recess 103 is formed on the bottom of the opening 102.
Next, as shown in FIG. 1C, a high-temperature oxide film HTO101 is deposited by CVD to a thickness of 150 nm, and then etched back, thereby removing the high-temperature oxide film HTO101 formed on the silicon oxide film SN102 and the bottom of the opening 102, while leaving the high-temperature oxide film HTO101 formed on the side faces of the opening 102, thereby forming side walls of the high-temperature oxide film HTO101 on the side faces of the opening 102. This reduces the inner diameter of the opening 102 to form an opening 104.
Next, as shown in FIG. 1D, the silicon oxide film SN102 and the high-temperature oxide film HTO101 are masked, and the polysilicon film PS101 is selectively removed by dry etching, thereby exposing the coupling oxide film COX101 at the bottom of the opening 104.
Next, as shown in FIG. 2A, arsenic (As) ions are implanted into the bottom of the opening 104, thereby forming an n+ diffusion region 105 on the surface of the silicon substrate 101. This n+ diffusion region 105 becomes the source.
Next, as shown in FIG. 2B, a high-temperature oxide film HTO102 is deposited on the entire face, and etched back so as to form side walls formed of high-temperature oxide film HTO102 along the side face of the opening 104. The etching back at this time removes the coupling oxide film COX101 at the bottom of the opening 104, so that the n+ diffusion region 105 of the silicon substrate 101 is exposed.
Next, as shown in FIG. 2C, a polysilicon film PS102 having a high concentration of As or P is deposited on the entire face, and the etched back, so as to fill in the opening 104 with the polysilicon film PS102. This forms a source plug connected to the n+ diffusion region 105 which is the source.
Next, as shown in FIG. 2D, wet etching is performed to remove the silicon nitride film SN102. This exposes the portions of the polysilicon film PS101 which were directly below the silicon nitride film SN102.
Next, as shown in FIG. 3A, the high-temperature oxide films HTO101 and HTO102 are masked, and the polysilicon film PS101 is dry-etched. Thus, the portions of the polysilicon film PS101 which were directly underneath the silicon nitride film SN102 (see FIG. 2D) are selectively removed. Note that the portions of the polysilicon film PS101 directly below the high-temperature oxide film HTO101 is not removed but remains. This remaining polysilicon film PS101 becomes the floating gate FG101. The form of the floating gate FG101 reflects the shape of the recess 103 (see FIG. 1B), and has a sharp ridge 106 formed at the edge farthest from the n+ diffusion region 105. This dry etching also removes part of the polysilicon film PS102.
Next, as shown in FIG. 3B, wet etching removes part of the exposed coupling oxide film COX101. At this time, the high-temperature oxide film HTO101 is also etched, so the width and height thereof is reduced somewhat. Consequently, the sharp ridge 106 of the floating gate FG101 is exposed.
Next, as shown in FIG. 3C, a high-temperature oxide film HTO103 is formed on the entire face. This covers the sharp ridge 106 of the floating gate FG101 with the high-temperature oxide film HTO103, and the high-temperature oxide film HTO103 serves as a tunneling oxide film.
Next, as shown in FIG. 3D, a polysilicon film PS103 is formed on the entire face and etched back, so as to form side walls of polysilicon film PS103 on the side portions of the side walls formed of the high-temperature oxide film HTO101 with the high-temperature oxide film HTO103 therebetween. The side wall becomes the control gate, serving as the word line.
Next, as shown in FIG. 4, the polysilicon films PS102 and PS103 and the high-temperature oxide film HTO101 are masked, and arsenic (As) ions are implanted, thereby forming an n+ diffusion region 107 at a region which is not directly below the polysilicon films PS102 and PS103 and the high-temperature oxide film HTO101 on the surface of the silicon substrate 101. This n+ diffusion region 107 becomes the drain, serving as the bit line. Subsequently, wiring is formed by normal CMOS processes, thereby fabricating the flash memory.
With the conventional flash memory, the floating gate FG101 has the sharp ridge 106, so the internal electric field intensity within the high-temperature oxide film HTO103 near the sharp ridge 106 rises (electrostatic focusing effect), and electrons are efficiently drawn from the sharp ridge 106 to the control gate formed of the polysilicon film PS103. Accordingly, in the event that the voltage Vw to be applied to the word line is the same (e.g., Vw=10 V), the erasing speed can be improved as compared to cases wherein the sharp ridge 106 has not been formed. Also, the voltage Vw can be reduced.
However, the above-described conventional technique has the following problems. As descried above, the silicon nitride film SN102 is dry-etched in the step shown in FIG. 1A, but a sufficient selection ratio (ratio of etching speeds) cannot be ensured between the silicon nitride film and the polysilicon, as shown in FIG. 1B, so the polysilicon film PS101 is over-etched, and the recess 103 is unavoidably formed. At this time, the degree of over-etching differs from one cell to another, so the shape of the recess 103 also differs from one cell to another.
With the conventional technique described above, the recess 103 is used to form the sharp ridge 106 of the floating gate FG101, so the shape of the sharp ridge 106, particularly the angle of the point, is very irregular. Consequently, there is irregularity in the behavior of the electrons drawn out from the floating gate FG101 due to the irregularity of the field intensity at the portion of the high-temperature oxide film HTO103 covering the sharp ridge 106. This means that the erasing properties such as erasing speed and the like differ from one cell to another in a single flash memory device. As a result, the actions of the flash memory are unstable, and the reliability is poor.